Job Detail

Job Description

CAD Engineer - EMIR Signoff Lead

Portland,Oregon,United States

Hardware

• Solid understanding of circuit design principles

• Experience in EM, IR, ESD, IVD (DVD), and SigEM analysis

• Methodology for transistor and gate level EMIR analysis for multiple modes, like: scan and dynamic modes, vectorless, vectored, jitter, package, electromigration, etc.

• Methodology for transistor and gate level SigEM analysis including static and dynamic

• In-depth knowledge of industry leading tools like Voltus-FI and Totem as well as Voltus and RedHawk

• Experience in developing CMOS analog and mixed signal designs is a plus

• Experience in simulating and verifying circuit performance and functionality a plus

• Power analysis experience is useful

• Strong understanding of CAD flows

• Proficiency in programming/scripting languages (Perl / Python / TCL)

• Excellent communication skills and ability to collaborate

Description

• Determine signoff criteria; work with technology and design teams - Participate in technology and design reviews - Develop and maintain signoff checks - Verify CAD flows are generating correct results (flow signoff) - Evaluate designs for signoff - Drive signoff reviews with design teams - Enablement of design teams on signoff infrastructure including page generation, build list maintenance, and enhancement request tracking - Signature file creation and management and delegation of signature responsibility - Milestone and signoff scheduling. Signature tracking - Ability to work in a demanding, collaborative environment

Education & Experience

MSEE with 7+ years of experience or BSEE with 10+ years of experience

Additional Requirements

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Job Detail

• Location:
  Portland, Oregon
• Company:
  Apple