Cellular SoC Power Engineer
Austin,Texas,United States
Hardware
Experience with ASIC low power micro-architecture and design, and solid understanding of Verilog and System Verilog.
Good understanding with script writing in Python or Perl.
Hands on experience with PTPX and Power Artist power analysis tools.
Familiarity with physical design tools for power optimization.
Advanced knowledge of SoC design and flow methodology.
Silicon validation / power measurement experience is a plus.
Strong interpersonal skills are a pre-requisite as you will collaborate with a lot of diverse groups.
Description
The main responsibility of this role is to drive Wireless/Cellular SOC low power micro- architecture definition, implementation and analysis. • Work with multi-functional teams including system architects and software teams to make micro-architectural design trade-offs for power versus performance as well as leakage versus active power. • Provide power improvement suggestions and collaborate a variety of teams to implement proposed power improvements. • Build and own the definition of exciting power use cases and their implementation in verification environments. • Analyze power data from multiple sources, identify power issues attributable to design, implementation or tool flows • Maintain and improve existing power modeling and analysis flows. • Keep track of the key QoR data from each step, including synthesis and P&R. • Provide power projections for future projects based on analysis.
Education & Experience
BSEE, MSEE or equivalent experience.
Additional Requirements
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