FPGA Design Engineer, Platform Architecture
Santa Clara Valley (Cupertino),California,United States
Hardware
Strong logic design background with ability to do RTL design and verification using Verilog/System Verilog.
Experience with High Level Synthesis with Vivado HLS, Catapult or Stratus. C/C++/SystemC knowledge for HLS.
Ability to develop scripts using Perl/Python for automating various flows.
Experience with FPGA tool flows (including Xilinx/Altera/Lattice) and bringup and debug of FPGA based designs.
Experience with industry-standard protocols (PCI Express, USB, Ethernet etc.)
Experience with common peripheral interfaces like I2C,SPI, high speed serial I/Fs etc.
Standout colleague with excellent social skills.
Ability to quickly pick up new concepts and chip in with innovative solutions.
Strong troubleshooting and analytical skills.
Description
Collaborate with cross-function teams (including electrical, mechanical and software) in order to define prototyping hardware to evaluate new technologies and features. Work independently and handle deliverables to align with project goals. Design and Verification using Verilog and System Verilog. Perform Synthesis/Place & Route, timing optimizations. Perform bring-up, debug and validation of designs to achieve the desired goals. Create thorough technical documents for each of the above steps. Develop state of the art processes and flows to accelerate design and validation of prototypes.
Education & Experience
BS EE/CE - MS or PhD Preferred
Additional Requirements
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